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19 tm august 1997 icm7231, ICM7232 numeric/alphanumeric triplexed lcd display drivers features ? icm7231 drives 8 digits of 7 segments with two independent annunciators per digit address and data input in parallel format ? ICM7232 drives 10 digits of 7 segments with two independent annunciators per digit address and data input in serial format ? all signals required to drive rows and columns of triplexed lcd display are provided ? display voltage independent of power supply ? on-chip oscillator provides all display timing ? total power consumption typically 200 w, maximum 500 w at 5v ? low-power shutdown mode retains data with 5 w typical power consumption at 5v, 1 w at 2v ? direct interface to high-speed microprocessors description the icm7231 and ICM7232 family of integrated circuits are designed to generate the voltage levels and switching wave- forms required to drive triplexed liquid-crystal displays. these chips also include input buffer and digit address decoding circuitry allowing six bits of input data to be decoded into 64 independent combinations of the output segments of the selected digit. the family is designed to interface to modern high- performance microprocessors and microcomputers and ease system requirements for rom space and cpu time needed to service a display. ordering information part number temp. range ( o c) package number of digits input format pkg. no. icm7231bfijl -25 to 85 40 ld cerdip 8 digit parallel f40.6 icm7231bfipl -25 to 85 40 ld pdip 8 digit parallel e40.6 ICM7232bfipl -25 to 85 40 ld pdip 10 digit serial e40.6 ICM7232cripl -25 to 85 40 ld pdip 10 digit serial e40.6 note: all versions intended for triplexed lcd displays. fn3161.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
20 pinouts icm7231bf (pdip, cerdip) top view ICM7232af, bf (pdip, cerdip) top view ICM7232cr (pdip) top view 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 cs v disp bp1 bp2 bp3 b 1, c 1, an 11 a 1, g 1, d 1 f 1, e 1, an 21 b 2, c 2, an 12 a 2, g 2, d 2 f 2, e 2, an 22 b 3, c 3, an 13 a 3, g 3, d 3 f 3, e 3, an 23 b 4, c 4, an 14 a 4, g 4, d 4 f 4, e 4, an 24 b 5, c 5, an 15 a 5, g 5, d 5 f 5, e 5, an 25 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 v dd a2 a1 a0 v ss bd3 bd2 bd1 bd0 an2 an1 f 8, a 8, an 28 a 8, g 8, d 8 b 8, c 8, an 18 f 7, e 7, an 27 a 7, g 7, d 7 b 7, c 7, an 17 f 6, e 6, an 26 a 6, g 6, d 6 b 6, c 6, an 16 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 data clock v disp bp1 bp2 bp3 b 1, c 1, an 11 a 1, g 1, d 1 f 1, e 1, an 21 b 2, c 2, an 12 a 2, g 2, d 2 f 2, e 2, an 22 b 3, c 3, an 13 a 3, g 3, d 3 f 3, e 3, an 23 b 4, c 4, an 14 a 4, g 4, d 4 f 4, e 4, an 24 b 5, c 5, an 15 a 5, g 5, d 5 f 5, e 5, an 25 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 v dd write input data input data accepted v ss b 6, c 6, an 16 a 6, g 6, d 6 f 6, e 6, an26 b 7, c 7, an 17 a 7, g 7, d 7 a 9, g 9, d 9 f 9, e 9, an 29 b 10, c 10, an 110 a 10, g 10, d 10 f 10, e 10, an 210 f 7, e 7, an 27 b 8, c 8, an 18 a 8, g 8, d 8 f 8, a 8, an 28 b 9, c 9, an 19 output input 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 data clock v disp bp1 bp2 bp3 b 1, c 1, an 11 a 1, g 1, d 1 f 1, e 1, an 21 b 2, c 2, an 12 a 2, g 2, d 2 f 2, e 2, an 22 b 3, c 3, an 13 a 3, g 3, d 3 f 3, e 3, an 23 b 4, c 4, an 14 a 4, g 4, d 4 f 4, e 4, an 24 b 5, c 5, an 15 a 5, g 5, d 5 f 5, e 5, an 25 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 v dd write input data input data accepted v ss b 6, c 6, an 16 a 6, g 6, d 6 f 6, e 6, an 26 b 7, c 7, an 17 a 7, g 7, d 7 a 9, g 9, d 9 f 9, e 9, an 29 b 10, c 10, an 110 a 10, g 10, d 10 f 10, e 10, an 210 f 7, e 7, an 27 b 8, c 8, an 18 a 8, g 8, d 8 f 8, a 8, an 28 b 9, c 9, an 19 output input icm7231, ICM7232
21 functional block diagrams icm7231 note: see figure 13 for display segment connections. segment line drivers 3 wide output latches 9 wide data decoder en d8 d7 d6 d5 d4 d3 d2 d1 bp1 bp2 bp3 cs v dd v h v l v disp on chip display voltage level generator pin 2 (input) address inputs data inputs f 2, e 2, an 22 a 2, g 2, d2 b 2, c2, an 12 f 1, e 1, an 21 a 1, g 1, d 1 b 1, c 1, an 11 common line drivers digit address decoder data input latches an1 bd0 bd2 an2 bd1 bd3 en address input latches en a2 a1 a0 one shot display timing generator 9 9 9 9 9 9 9 9 9 9 icm7231, ICM7232
22 ICM7232 note: see figures 13 and 14 for display segment connections. functional block diagrams (continued) segment line drivers 3 wide output latches 9 wide data decoder en d10 d7d6d5d4d3d2d1 bp1 bp2 bp3 v dd v h v l v disp on chip display voltage level generator pin 2 (input) shift register data common line drivers digit address decoder an1 bd0 bd2 an2 bd1 bd3 serial input contol logic display timing generator 9 9 d9 d8 9 9 9 9 9 9 9 9 9 input data clock write input data accepted input output shifts right to left on rising edge of data clock clock data a2 a1 a0 a3 f 2, e 2, an 22 a 2, g 2, d2 b 2, c2, an 12 f 1, e 1, an 21 a 1, g 1, d 1 b 1, c 1, an 11 icm7231, ICM7232
23 absolute maximum ratings thermal information supply voltage (v dd - v ss ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5v input voltage (note 1) . . . . . . . . . . . . . . . . . . . v ss - 0.3 v in 6.5 display voltage (note 1). . . . . . . . . . . . . . . . . . . .0.3 v disp +0.3 operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . -25 o c to 85 o c thermal resistance (typical, note 2) ja ( o c/w) jc ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . 60 n/a cerdip package . . . . . . . . . . . . . . . . 50 12 maximum junction temperature ceramic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 o c plastic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering, 10s) . . . . . . . . . . . . 300 o c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. notes: 1. due to the scr structure inherent in these devices, connecting any display terminal or the display voltage terminal to a volt age outside the power supply to the chip may cause destructive device latchup. the digital inputs should never be connected to a voltage le ss than -0.3v below ground, but maybe connected to voltages above v dd but not more than 6.5v above v ss . 2. ja is measured with the component mounted on an evaluation pc board in free air. electrical specifications v+ = 5v +10%, v ss = 0v, t a = -25 o c to 85 o c, unless otherwise specified parameter test conditions min typ max units power supply voltage, v dd 4.5>45.5 v data retention supply voltage, v dd guaranteed retention at 2v 2 1.6 - v logic supply current, i dd current from v dd to ground excluding display. v disp = 2v -30100 a shutdown total current, i s v disp pin 2 open - 1 10 a display voltage range, v disp v ss v disp v dd 0-v dd v display voltage setup current, i disp v disp = 2v, current from v dd to v disp on- chip -1530 a display voltage setup resistor value, r d- isp one of three identical resistors in string 40 75 - k ? dc component of display signals (sample test only) - 1 / 4 1% (v dd - v disp ) display frame rate, f disp see figure 5 60 90 120 hz input low level, v il icm7231, pins 30 - 35, 37 - 39, 1 ICM7232, pins 1, 38, 39 (note 2) --0.8 v input high level, v ih 2.0 - - v input leakage, i ilk - 0.1 1 a input capacitance, c in -5- pf output low level, v ol pin 37, ICM7232, i ol = 1ma - - 0.4 v output high level, v oh v dd = 4.5v, i oh = -500 a4.1--v operating temperature range, t op industrial range -25 - +85 o c ac specifications v dd = 5v +10% v ss = 0v, -25 o c to 85 o c parameter test conditions min typ max units parallel input (icm7231) see figure 1 chip select pulse width, t cs (note 1) 500 350 - ns address/data setup time, t ds (note 1) 200 - - ns address/data hold time, t dh (note 1) 0 -20 - ns inter-chip select time, t ics (note 1) 3 - - s serial input (ICM7232) see figures 2, 3 data clock low time, t cl (note 1) 350 - - ns data clock high time, t cl (note 1) 350 - - ns data setup time, t ds (note 1) 200 - - ns data hold time, t dh (note 1) 0 -20 - ns write pulse width, t wp (note 1) 500 350 - ns write pulse to clock at initialization, t wll (note 1) 1.5 - - s icm7231, ICM7232
24 data accepted low output delay, t odl (note 1) - 200 400 ns data accepted high output delay, t odh (note 1) - 1.5 3 s write delay after last clock, t cws (note 1) 350 - - ns table of features type number output code annunciator locations input output icm7231bf code b both annunciators on bp3 parallel entry, 4-bit data, 2-bit annunciators, 3-bit address 8 digits plus 16 annunciators ICM7232af hexadecimal both annunciators on bp3 serial entry, 4-bit data, 2-bit annunciators, 4-bit address 10 digits plus 20 annunciators ICM7232bf code b ICM7232cr code b 1 annunciator bp1 1 annunciator bp3 terminal definitions terminal pin no. description function icm7231 parallel input numeric display an1 30 annunciator 1 control bit high = on an2 31 annunciator 2 control bit low = off see table 3 bd0 32 least significant 4-bit binary data inputs input data (see table 1) high = logical one (1) low = logical zero (0) bd1 33 bd2 34 bd3 35 most significant a0 37 least significant 3-bit digit address inputs input address (see table 2) a1 38 a2 39 most significant cs 1 data input strobe/chip select (note 2) trailing (positive going) edge latches data, causes data input to be decoded and sent out to addressed digit ICM7232 serial data and address input data input 38 data+ address shift register input high = logical one (1) low = logical zero (o) write input 39 decode, output, and reset strobe when data accepted output is low, positive going edge of write causes data in shift register to be decoded and sent to ad- dressed digit, then shift register and control logic to be reset. when data accepted output is high, positive going edge of write trig- gers reset only. data clock input 1 data shift register and control logic clock positive going edge advances data in shift register. ICM7232: elev- enth edge resets shift register and control logic. data accepted output 37 handshake output output low when correct number of bits entered into shift register. all devices display voltage v dlsp 2 negative end of on-chip resistor string used to generate intermediate voltage levels for display. shutdown input. display voltage control. when open (or less than 1v from v dd ) chip is shutdown; oscillator stops, all display pins to v dd . common line driver outputs 3, 4, 5 drive display commons, or rows segment line driver outputs 6 - 29 6 - 35 (on icm7231) (on ICM7232) drive display segments, or columns. ac specifications v dd = 5v +10% v ss = 0v, -25 o c to 85 o c parameter test conditions min typ max units icm7231, ICM7232
25 v dd 40 chip positive supply v ss 36 chip negative supply notes: 1. for design reference only, not 100% tested. 2. cs has a special ?mid-level? sense circuit that establishes a test mode if it is held near 3v for several ms. inadvertent trigger ing of this mode can be avoided by pulling it high when inactive, or ensuring frequent activity. terminal definitions terminal pin no. description function timing diagrams figure 1. icm7231 input timing diagram t dh t cs t ds do not care cs input data address input address and data inputs valid address and data inputs valid t ics icm7231, ICM7232
26 figure 2. ICM7232 one digit input timing diagram, writing both annunciators timing diagrams data clock input (per bit of data) data input write input resets shift register and input control logic when data accepted high decodes and stores data, resets shift register and logic when data accepted is low do not care eleventh clock with no write pulse resets sr + logic t ci t ci t ds t dh t odl t wll t wp t cws t wp data accepted output 1 2 3 8 9 10 t odl an2 data valid bd0 data valid a2 data valid t odh a3 data valid a1 data valid an1 data valid icm7231, ICM7232 maxcmos ? is a registered trademark of intersil corporation.
27 icm7231 family description the icm7231 drives displays with 8 seven-segment digits with two independent annunciators per digit, accepting six data bits and three digit address bits from parallel inputs con- trolled by a chip select input. the data bits are subdivided into four binary code bits and two annunciator control bits. the ICM7232 drives 10 seven-segment digits with two inde- pendent annunciators per digit. to write into the display, six bits of data and four bits of digit address are clocked serially into a shift register, then decoded and written to the display. input levels are ttl compatible, and the data accepted output on the serial input devices will drive one lsttl load. the intermediate voltage levels necessary to drive the dis- play properly are generated by an on-chip resistor string, and the output of a totally self-contained on-chip oscillator is used to generate all display timing. all devices in this family have been fabricated using intersil? maxcmos ? process and all inputs are protected against static discharge. triplexed ( 1 / 3 multiplexed) liquid crystal displays figure 4 shows the connection diagram for a typical 7-segment display with two annunciators such as would be used with an icm7231 or ICM7232 numeric display driver. figure 5 shows the voltage waveforms of the common lines and one segment line, chosen for this example to be the ?a, g, d? segment line. this line intersects with bp1 to form the ?a? segment, bp2 to form the ?g? segment and bp3 to form the ?d? segment. figure 5 also shows the waveform of the ?a, g, d? segment line for four different on/off combinations of the ?a?, ?g? and ?d? segments. each intersection (segment or annunciator) acts as a capacitance from segment line to common line, shown schematically in figure 6. figure 7 shows the voltage across the ?g? segment for the same four combinations of on/off segments used in figure 5. figure 3. ICM7232 input timing diagram, leaving both annunciators off timing diagrams data clock input data input write input resets shift register and input control logic when data accepted high decodes and stores data, resets shift register and logic when data accepted is low do not care t ci t ci t ds t dh t wll t wp data accepted output 1 2 3 7 8 bd0 data valid t cws t wp t odh t odi bd1 data valid bd2 data valid a2 data valid a3 data valid an1 enter first an2 bd0 bd1 bd2 bd3 a0 a1 a2 a3 enter last ICM7232 write order a b c d f g e bp1 bp2 bp3 an 2 an 1 backplane connections a b c d f g e segment lines an 2 an 1 segment line connections figure 4. connection diagrams for typical 7-segment displays icm7231, ICM7232
28 the degree of polarization of the liquid crystal material and thus the contrast of any intersection depends on the rms voltage across the intersection capacitance. note from figure 7 that the rms off voltage is always v p /3 and that the rms on voltage is always 1.92v peak /3. for a 1 / 3 multiplexed lcd, the ratio of rms on to off voltages is fixed at 1.92, achieving adequate display contrast with this ratio of applied rms voltage makes some demands on the liquid crystal material used. v dd v h v l v disp v dd v h v l v disp v dd v h v l v disp v dd v h v l v disp v dd v h v l v disp v dd v h v l v disp v dd v h v l v disp bp1 bp2 bp3 all on a , g on d off a segment on a , d off segment line all off 1 2 3 1 2 3 v p v dd v h v l v disp on chip resisto r string ~ 75k ? ~ 75k ? ~ 75k ? input common line waveforms typical segment line waveforms pin 2 notes: 1. 1, 2, 3, - bp high with respect to segment. 2. 1, 2, 3, - bp low with respect to segment. 3. bp1 active during 1, and 1. 4. bp2 active during 2, and 2. 5. bp3 active during 3, and 3. figure 5. display voltage waveforms bp1 bp2 bp3 f e an 2 a g d b c an 1 segment lines figure 6. display schematic 1 2 3 1 2 3 all on a, g on d off a segment on a, d off all off +vp 0 -vp +vp 0 -vp +vp 0 -vp +vp 0 -vp vp = (v+) - vdisp v rms vp 3 -------- v rms off == v rms 11 3 ---------- vp 3 -------- v rms on == notes: 1. 1, 2, 3, - bp high with respect to segment. 2. 1, 2, 3, - bp low with respect to segment. 3. bp1 active during 1, and 1. 4. bp2 active during 2, and 2. 5. bp3 active during 3, and 3. figure 7. voltage waveforms on segment g(v g ) voltage contrast ratio v rms on v rms off ----------------------------- - 11 3 ---------- 1.92 === icm7231, ICM7232
29 figure 8 shows the curve of contrast versus applied rms volt- age for a liquid crystal material tailored for v peak = 3.1v, a typical value for 1 / 3 multiplexed displays in calculators. note that the rms off voltage v peak /3 1v is just below the ?threshold? voltage where contrast begins to increase. this places the rms on voltage at 2.1v, which provides about 85% contrast when viewed straight on. all members of the icm7231 and ICM7232 family use an internal resistor string of three equal value resistors to generate the volt- ages used to drive the display. one end of the string is con- nected on the chip to v dd and the other end (user input) is available at pin 2 (v disp ) on each chip. this allows the display voltage input (v disp ) to be optimized for the particular liquid crys- tal material used. remember that v peak = v dd - v disp and should be three times the threshold voltage of the liquid crystal material used. also it is very important that pin 2 never be driven below v ss . this can cause device latchup and destruction of the chip. temperature effects and temperature compensation the performance of the lcd material is affected by tempera- ture in two ways. the response time of the display to changes of applied rms voltage gets longer as the display tempera- ture drops. at very low temperatures (-20 o c) some displays may take several seconds to change a new character after the new information appears at the outputs. however, for most applications above 0 o c this will not be a problem with avail- able multiplexed lcd materials, and for low-temperature applications, high-speed liquid crystal materials are available. at high temperature, the effect to consider deals with plastic materials used to make the polarizer. some polarizers become soft at high temperatures and per- manently lose their polarizing ability, thereby seriously degrading display contrast. some displays also use sealing materials unsuitable for high temperature use. thus, when specifying displays the following must be kept in mind: liquid crystal material, polarizer, and seal materials. a more important effect of temperature is the variation of threshold voltage. for typical liquid crystal materials suitable for multiplexing, the peak voltage has a temperature coefficient of -7 to -14mv/ o c. this means that as temperature rises, the thresh- old voltage goes down. assuming a fixed value for v p , when the threshold voltage drops below v peak /3 off segments begin to be visible. figure 9 shows the temperature dependence of peak voltage for the same liquid crystal material of figure 8. for applications where the display temperature does not vary widely, v peak may be set at a fixed voltage chosen to make the rms off voltage, v peak /3, just below the threshold voltage at the highest temperature expected. this will prevent off segments turning on at high temperature (this at the cost of reduced contrast for on segments at low temperatures). for applications where the display temperature may vary to wider extremes, the display voltage v disp (and thus v peak ) may require temperature compensation to maintain sufficient contrast without off segments becoming visible. display voltage and temperature compensation these circuits allow control of the display peak voltage by bringing the bottom of the voltage divider resistor string out at pin 2. the simplest means for generating a display voltage suitable to a particular display is to connect a potentiometer from pin 2 to v ss as shown in figure 10. a potentiometer with a maximum value of 200k ? should give sufficient range of adjustment to suit most displays. this method for generating display voltage should be used only in applications where the temperature of the chip and display won?t vary more than 5 o c ( 9 o f), as the resistors on the chip have a positive tem- perature coefficient, which will tend to increase the display peak voltage with an increase in temperature. the display voltage also depends on the power supply voltage, leading to tighter tolerances for wider temperature ranges. applied voltage (v rms ) contrast (%) 100 90 80 70 60 50 40 30 20 10 0 t a = 25 o c = -10 o = -30 o = 0 v on = 2.1v 01234 = +10 o v off = 1.1v rms 0- 0+ figure 8. contrast vs applied rms voltage ambient temperature ( o c) 6 5 4 3 2 1 0 -10 0 10 20 30 40 50 peak voltage for 90% contrast (on) peak voltage for 10% contrast (off) peak voltage figure 9. temperature dependence of lc threshold icm7231, ICM7232
30 figure 11a shows another method of setting up a display voltage using five silicon diodes in series. these diodes, 1n914 or equivalent, will each have a forward drop of approximately 0.65v, with approximately 20 a flowing through them at room temperature. thus, 5 diodes will give 3.25v, suitable for a 3v display using the material properties shown in figures 4 and 5. for higher voltage displays, more diodes may be added. this circuit provides reasonable temperature compensation, as each diode has a negative temperature coefficient of -2mv/ o c; five in series gives -10mv/ o c, not far from optimum for the material described. the disadvantage of the diodes in series is that only integral multiples of the diode voltage can be achieved. the diode voltage multiplier circuit shown in figure 11b allows fine- tuning the display voltage by means of the potentiometer; it likewise provides temperature compensation since the tem- perature coefficient of the transistor base-emitter junction (about -2mv/ o c) is also multipled. the transistor should have a beta of at least 100 with a collector current of 10 a. the inexpensive 2n2222 shown in the figure is a suitable device. for battery operation, where the display voltage is generally the same as the battery voltage (usually 3 - 4.5v), the chip may be operated at the display voltage, with v dlsp connected to v ss . the inputs of the chip are designed such that they may be driven above v dd without damaging the chip. this allows, for example, the chip and display to operate at a regulated 3v, and a microprocessor driving its inputs to operate with a less well controlled 5v supply. (the inputs should not be driven more than 6.5v above gnd under any circumstances.) this also allows temperature compensation with the icl7663s, as shown in figure 12. this circuit allows independent adjustment of both voltage and temperature compensation. description of operation parallel input of data and address (icm7231) the parallel input structure of the icm7231 device is organized to allow simple, direct interfacing to all micropro- cessors, (see the functional block diagram). in the icm7231, address and data bits are written into the input latches on the rising edge of the chip select input. the rising edge of the chip select also triggers an on-chip pulse which enables the address decoder and latches the decoded data into the addressed digit/character outputs. the timing requirements for the parallel input device are shown in figure 1, with the values for setup, hold, and pulse width times shown in the ac specifications section. note that there is a minimum time between chip select pulses; this is to allow suf- ficient time for the on-chip enable pulse to decay, and ensures that new data doesn?t appear at the decoder inputs before the decoded data is written to the outputs. serial input of data and address (ICM7232) the icm3232 trades six pins used as data inputs on the icm7231 for six more segment lines, allowing two more 9-segment digits. this is done at the cost of ease in interfac- ing, and requires that data and address information be entered serially. refer to functional block diagram and tim- ing diagrams, figures 2 and 3. the interface consists of four pins: data input, data clock input, write input and data accepted output. the data present at the data input is clocked into a shift register on the rising edge of the open 200k ? 10nf +5 icm7231 ICM7232 v disp 240 36 figure 10. simple display voltage adjustment v dd 40k ? 10nf +5 icm7231 ICM7232 v disp 240 36 1n914 diodes figure 11a. string of diodes v dd 40k ? 10nf +5 icm7231 ICM7232 v disp 240 36 200k ? potentiometer 2n2222 figure 11b. transistor-multiplier figure 11. diode-based temperature compensation v in + v out1 v out2 icl7663s v set v tc gnd data bus icm7233 v disp gnd 1.8m ? 300k ? 2.7m ? logic system processor, +5v v dd etc. figure 12. flexible temperature compensation icm7231, ICM7232
31 data clock input signal, and when the correct number of bits has been shifted into the shift register (8 in the ICM7232), the data accepted output goes low. follow- ing this, a low-going pulse at the write input will trigger the chip to decode the data and store it in the output latches of the addressed digit/character. after the data is latched at the outputs, the shift register and the control logic are reset, returning the data accepted output high. after this occurs, a pulse at the write input will not change the out- puts, but will reset the control logic and shift register, assuring that each data bit will be entered into the correct position in the shift register depending on subsequent data clock inputs. the shift register and control logic w ill also be reset if too many data clock input edges are received; this pre- vents incorrect data from being decoded. in the ICM7232, the eleventh clock resets the shift register and control logic. the recommended procedure for entering data is shown in the serial input timing diagram, figure 2. first, when data accepted is high, send a write pulse. this resets the shift register and control logic and initializes the chip for the data input sequence. next clock in the appropriate number of correct data and address bits. the data accepted output may be monitored if desired, to determine when the chip is ready to output the decoded data. when the correct number of bits has been entered, and the data accepted output is low, a pulse at write will cause the data to be decoded and stored in the latches of the addressed digit/character. the shift register and control logic are reset, causing data accepted to return high, and leaving the chip ready to accept data for the next digit/char- acter. note that for the ICM7232 the eleventh clock resets the shift register and control logic, but the data accepted output goes low after the eighth clock. this allows the user to abbreviate the data to eight bits, which will write the correct character to the 7-segment display, but will leave the annun- ciators off, as shown in figure 3. if only an2 is to be turned on, nine bits are clocked in; if an1 is to be turned on, all ten bits are used. the data accepted output will drive one low-power schottky ttl input, and has equal current drive capability pulling high or low. note that in the serial input devices, it is possible to address digits/characters which don?t exist. as shown in table 2 when an incorrect address is applied together with a write pulse, none of the outputs will be changed. display fonts and output codes the standard versions of the icm7231 and ICM7232 chips are programmed to drive a 7-segment display plus two annuncia- tors per digit. see table 3 for annunciator input controls. the ?a? and ?b? suffix chips place both annunciators on bp3. the display connections for one digit of this display are shown in figure 13. the ?a? devices decode the input data into a hexadecimal 7-segment output, while the ?b? devices supply code b outputs (see table 1). the ?c? devices place the left hand annunciator on bp1 and the right hand annunciator (usually a decimal point) on bp3. (see figure 14). the ?c? devices provide only a ?code b? output for the 7 segments. table 1. blnary data decoding icm7231 and ICM7232 code input display output bd3 bd2 bd1 bd0 hex code b 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 icm7231, ICM7232
32 1111 blank table 2. address decoding (icm7231 and ICM7232) code input display output ICM7232 only a3 a2 a1 a0 digit selected 0 000 d1 0 001 d2 0 010 d3 0 011 d4 0 100 d5 0 101 d6 0 110 d7 0 111 d8 1 000 d9 1 001 d10 1 0 1 0 none 1 0 1 1 none 1 1 0 0 none 1 1 0 1 none 1 1 1 0 none 1 1 1 1 none table 3. annunclator decoding code input display output an2 an1 icm7231a and icm7231b ICM7232a and ICM7232b both annunciators on bp3 icm7231c ICM7232c an2 annunciator bp1 an1 annunclator bp3 00 01 table 1. blnary data decoding icm7231 and ICM7232 code input display output bd3 bd2 bd1 bd0 hex code b 10 11 table 3. annunclator decoding code input display output icm7231, ICM7232
33 ) compatible displays compatible displays are manufactured by: g.e. displays inc., beechwood, ohio (216) 831-8100 (#356e3r99hj) epson america inc., torrance ca (model numbers ldb726/7/8). seiko instruments usa inc., torrance ca (custom displays) crystaloid, hudson, oh a b c d f g e bp1 bp2 bp3 an 2 an 1 backplane connections segment lines segment line connections figure 13. icm7231 and ICM7232 display fonts (?a? and ?b? suffix versions a b c d f g e segment lines bp1 bp2 bp3 an 2 an 1 (note 1) backplane connections segment lines (note 1) segment line connections note: 1. annunciators can be: , , , -arrows that point to information printed around the display opening etc., whatever the designer display opening etc., whatever the de- signer chooses to incorporate in the liquid crystal display. figure 14. icm7231 display fonts (?c? suffix versions) stop go icm7231, ICM7232
34 typical applications note: the annunciators show function and the decimal points indicate the range of the current operation. the system can be effic iently battery operated. figure 15. 10mhz frequency/period pointer with lcd display period interval test freq. ratio frequency unit over range input a input b icm7226a d1 - d8 bcd dp function range cd4532 gs d0 - d7 +5v cs icm7231cf bd0 - 3 an2 an1 a0 a1 a2 q0 q1 q2 e1 v+ 1 f 10k 27
35 figure 16. ?forward? pin orientation and display connections typical applications (continued) x yz x yz x yz x yz x yz x yz x yz x yz icm7231af and icm7231bf top view com 1 com 2 com 3 to input d8 d7 d6 d5 d4 d3 d2 d1
36 figure 17. ?reverse? pin orientation and display connections typical applications (continued) x yz x yz x yz x yz x yz x yz x yz x yz ICM7232cr top view com 1 com 2 com 3 to input d8 d7 d6 d5 d4 d3 d2 d1 pcb traces under package select no forward stop x yz x yz wait go d9 d10
37 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com sales office headquarters north america intersil corporation 7585 irvine center drive suite 100 irvine, ca 92618 tel: (949) 341-7000 fax: (949) 341-7123 intersil corporation 2401 palm bay rd. palm bay, fl 32905 tel: (321) 724-7000 fax: (321) 724-7946 europe intersil europe sarl ave. william graisse, 3 1006 lausanne switzerland tel: +41 21 6140560 fax: +41 21 6140579 asia intersil corporation unit 1804 18/f guangdong water building 83 austin road tst, kowloon hong kong tel: +852 2723 6339 fax: +852 2730 1433 icm7231, ICM7232

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